Switching speed of transistors and diodes improve over each technology generation of shrinking geometries and increasing integration density or scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs). As per International Technology Roadmap for Semiconductor (ITRS) for the year 2010, the cut-off frequency of switching is expected to be of the order of 600 GHZs in 16 nm CMOS technology leading to the availability of hundreds of GHZs bandwidth in the near future.
ICs are networks/circuits in packages interconnecting thousands or millions or billions of discrete electronic components like transistors, diodes, resistors, capacitors etc. depending on Small Scale Integration (SSI) or Large Scale Integration (LSI) or Very Large Scale Integration (VLSI). However, increasing clock frequency for operation of ICs in a push for faster computation, power lost as heat in components like transistors due to switching, and Metallic Interconnects (MIs) due to skin effect, and propagation delays due to Resistance-Capacitance (RC) time constants in MIs connecting discrete electronic components increases particularly in LSI and VLSI degrading performance. Increasing clock frequency for the operation of digital ICs, increases the self-inductance (L) and therefore self-reactance (XL=2πfL) of MIs. However, central core portion of the MI experience greater L and 2πfl pushing current to flow through the outer periphery of MI known as the skin effect. Because of the skin effect, pulsating current flowing through MIs experience increased Impedance (R+jXL), and therefore increased I2R losses as heat in MIs.
Modern computing apparatus is composed of various ICs mounted on Mother Printed Circuit Board and if required additional add on Printed Circuit Boards (PCBs). PCBs usually of plastic material printed with traces of copper connecting various discrete components and pins of ICs, wherein copper traces are narrow, densely laid for communication of data, addresses, and control signals, and power supply to and from various ICs. Again, increasing frequency of operation of ICs in a push for faster computation, RC time constants of, power lost as heat due to skin effect in, and crosstalk called Inter Symbol Interference (ISI) due to parasitic inductances (L) among, long usually copper MIs connecting ICs increases degrading performance of an apparatus or a device or a system.
Therefore, global clock frequency and data rates within/intra and among/inter IC chips are limited to below about 6 GHZs. Scaling of MIs along with scaling of ICs in LSI/VLSI has degraded the performance of the LSI/VLSI in terms of operating clock frequency and data rates, and power consumption. With the increasing integration density and cut-off switching frequency of transistors in CMOS ICs, the MIs technology is emerging as a major bottleneck to the performance improvement of VLSI such as System-on-Chip (SoC), System-in-Package (SiP), and Network-on-Chip (NoC). This performance bottleneck is due to the global interconnection delays becoming significantly larger than the gate switching delays. Carbon nano-materials based Carbon Nano-Tubes (CNTs) and Graphene Nano-Ribbons (GNRs) are emerging as next-generation interconnect technology referred to as Carbon Interconnects (CIs) that has the potential to resolve the most problems of MIs. However, according to ITRS, only material innovations like CNTs and GNRs will lead to a brick wall that can only be overcome by radically different interconnect architectures based on other forms of technology scaling.
The MCA has evolved to have as many number of units of shared memory as number of processors. This is in order to facilitate simultaneous access of different units of shared memory by different processors for reducing latency and contention for shared memory. This approach has followed from FIG. 4 (FIG. 1a in this application) of the Best Possible Parallel Computer Architecture (BPPCA) claimed in the technologically disruptive U.S. Pat. No. 7,788,051 and Canadian Patent #2564625 titled “Method and Apparatus for Parallel Loadflow Computation for Electrical Power System”, where each processor has been shown to connect to a box of shared memory leading to an idea that shared memory can be divided into as many SMUs as the number of processors, and then provide interconnect to increase shared memory bandwidth. Canadian Patent #2564625 provides figures each completely contained in a single A4 size paper as originally provided by this inventor. So far the trend has been to put as many processors along with their Private Memories (PMs) and SMUs on a single chip with MIs and associated switches constituting what is called System on Chip (SoC). However, this arrangement can introduce substantial delays in accessing data from a SMU located at the other end across the chip by a processor at the one end, because data has to take several ‘hops’ through MIs and associated switches.
Parallel Gauss-Seidel-Patel Loadflow (PGSPL) when implemented on BPPCA claimed in the U.S. Pat. No. 7,788,051 and the Canadian Patent #2564625 titled “Method and Apparatus for Parallel Loadflow Computation for Electrical Power System”, ignoring all communication delays was estimated to speed-up by a factor of 10 for the first time in the parallel computation history, and that marked the beginning of the new era of computer technology. Historically, parallel computing produced speed-up at the most about 3-times. Any attempt to further speed-up by a factor greater than 3 was not successful even by increasing number of computers in parallel. The speed-up/scaling bottleneck was due to the techniques of decomposing a big computational problem into small sub-problems and the parallel computer architecture were not very well tuned, requiring huge moving around of computational data. The PGSPL method and BPPCA are very well tuned for minimum communication and synchronization requirements, and almost removed the speed-up/scaling bottleneck bringing about the state of “NIRVANA” for parallel computing in general. The minimum synchronization requirement is realized by making parallel processing locally asynchronous and globally synchronous. The BPPCA is scalable in the sense that it can have just two processors to thousands of processors all working in parallel. What followed was proliferation of many/multi-core computers, supercomputers with massive number crunching capabilities; massively parallel cloud computing machines or data centres. The envelop of technology is being pushed towards utility computing and ultimately putting all automated cloud computing machines (MCAs) in the outer space or on the other planets preferably on the Moon to begin with as per the case made by this inventor in his Canadian patent application #2743882, titled “System of Internet for Information/Data Processing, Storage, and Retrieval” completed on May 28, 2012.
Modern complex Electrical Power Utility System is composed of millions of tiny light bulbs to thousands of huge motors and generators all connected in parallel for operational convenience in the sense that each component from tiny light bulb to huge motor/generator can be individually turned on/off without disturbing the rest of the system. The evolution of single generator supplying single light bulb or a group of light bulbs into the modern complex Electrical Power Utility System is believed to have taken more than a century.
All automated cloud computing machines can be placed in the outer space or on the other planets preferably on the Moon to begin with for the following reasons.    1. Traditionally, scientists/engineers thought hard about the possibility of generating electricity in the outer space and transmitting on the earth for our use. Huge cloud computing machines consume lots of electricity that can be generated in the outer space and used there for running the cloud computing machines by deploying them in the outer space, and connecting them through wireless links to earth stations, which are connected to internet. Resources required for generating electricity for running the cloud computing machines and its impact on environment on the earth can be saved.    2. While machines can live, and work almost anywhere, life as we know it cannot be sustained in the outer space unless we learn to live there through technological innovations.    3. So far, Earth is the only planet known to be capable of sustaining life. Even in the desert precious air is available and water can be managed from other areas. Real estate earth is at premium for life and must not be spoiled as far as possible particularly when the cloud computing machines are capable of being deployed in the outer space.    4. The Moon to begin with provides naturally stable platform in the outer space for deployment of huge cloud computing machines. The Moon futuristically can be visualized as knowledge/information/data processing/storage/retrieval warehouse/library for humans on the earth.    5. Peeking deep into the future, the first thing needed is to construct a space highway when we are ready to travel deep into the outer space. The cloud computing machines can be used as mile (in terms of space distances) stones on the space highway. Spaceship of the kind of enterprise spaceship of Star Trek could be utilized in almost never ending process of constructing the space highway deeper and deeper into the outer space and deploying the cloud computing machines as mile stones. Travel on the already constructed space highway could be ‘Travel Light’ because new spaceship will not be required to carry bulky computing machines on board.    6. The concept of the cloud computing machines as mile stones or any other similar can be used in making highways/railways on the earth intelligent/smart.
High Performance Computing (HPC) or Supercomputing has found its way into mainstream following recent advances in parallel computing technologies particularly influenced by developments of U.S. Pat. No. 7,788,051. Every advance in computing technology has always been followed by increased expectations and demands for enhanced computational power. Usually the domain of science and technology, HPC has become increasingly pervasive among industries, businesses, and governments. Wireless communication in atmospheric free space is regulated by governments and requires licensing and standardization of a range of frequencies (a spectrum) for a particular use. This invention is about Wireless Interconnect (WLI) comprising Transceiver-Antenna (Transmitter-Receiver-Antenna) TRA mounted/fabricated/integrated/embedded on each of the multiprocessors and shared resources, and electromagnetically shielded and sealed confined free space within Metallic Enclosure (ME) housing MCA.
As per statements in US patent application publication 2012/0331269 titled “Geodesic Massively Parallel Computer”, different modern MCA share similar packaging, construction, and connectivity implementation hierarchy. That is: assemble component ICs onto PCBs, PCBs into racks, racks into cabinets, and cabinets into rooms. Typical communication channels are printed circuits on boards and backplanes, with electrical and fibre optic cabling running over longer distances. Processor-clusters communication in and between cabinets of massively parallel systems is typically cabled packet switched networks such as Infiniband or Ethernet. So far, all the arrangements have been the use of various physical interconnects networks for multiple processors, multiple SMUs, multiple inputs/outputs (I/Os) and other shared resources in MCA. Physical topologies of interconnection networks are typically star, ring, mesh, torus, hypercube, spherical hypercube, and other variants including interconnect controlled by routing and switching network as per FIG. 1b and FIG. 1c. 
Further, The current status of the rewritable Magneto-Optical (MO) and Optical (O) memories is that they are available in the form of rewritable Compact Disks (CD-RWs) and Digital Video Disks (DVD-RWs) and they need to be rotated using CD/DVD-drives in order to be able to read from and written to by a computer.